1. Field of the Invention
The present invention relates generally to spread spectrum communication systems, and more particularly to soft-decision chip sequence timing detection of a code division multiple access (CDMA) communication receiver for synchronizing to a received spread data sequence.
2. Description of the Related Art
In a prior art CDMA receiver, a lowpass-filtered spread spectrum data sequence is over-sampled at intervals Tc/L to increase its timing information and stored in a buffer memory, where Tc is the chip intervals and L is an integer greater than unity. A set of data samples stored in locations spaced from each other by chip intervals Tc but spaced from corresponding data samples of adjacent sets by intervals Tc/L is successively read out of the memory for detecting a match or mismatch with the despreading chip sequence of the receiver. If they match, the read data samples are selected as a synchronized data sequence and despread with the chip sequence and other data samples over-sampled during the same chip interval are discarded. However, the amount of memory required for buffering the over-sampled data is substantial and a large processing delay is introduced. This long processing time is undesirable when signals are transmitted in bursts.
On the other hand, Japanese Laid-Open Patent Specification Hei-9-321734 discloses an interference canceller CDMA communication receiver using a tapped-delay line filter for cancelling undesired signals with orthogonal tap weight coefficients and detecting a desired signal on which threshold decision is made. To eliminate the otherwise required training sequence, the tap weight coefficients are updated with a decision error and the vector of the updated coefficients is constrained to a plane which is orthogonal to a vector of the chip sequence. However, the chip sequence must be precisely synchronized to the received data sequence.
It is therefore an object of the present invention to provide a CDMA communication receiver which performs soft-decision chip sequence timing detection in a short processing time using a small memory.
According to a first aspect of the present invention, there is provided a CDMA communication receiver comprising a memory for storing chip samples representing amplitudes of a chip sequence sampled at intervals smaller than chip intervals of the chip sequence. Sync search and tracking circuitry is provided for reading, from the memory, a set of chip samples spaced from each other by the chip intervals and spaced from corresponding chip samples of adjacent sets by the smaller intervals, and detecting a match or mismatch between the read chip samples and an incoming data sequence. If they match, it is determined that the read chip samples is a synchronized chip sequence. Otherwise, a next set of chip samples is read from the memory for making a further test between the next set and the incoming data sequence. A despreading filter despreads the incoming data sequence with the synchronized chip sequence.
According to a second aspect of the present invention, there is provided a CDMA communication receiver comprising a memory for storing chip samples representing amplitudes of a chip sequence sampled at intervals smaller than chip intervals of the chip sequence and sync search and tracking circuitry for reading, from the memory, a set of chip samples spaced from each other by the chip intervals and spaced from corresponding chip samples of adjacent sets by the smaller intervals, and detecting a match or mismatch between the read chip samples and an incoming data sequence. If they match, the read chip samples is determined as a synchronized chip sequence. Otherwise, a next set of chip samples is read from the memory for making a further test between the next set and the incoming data sequence. A tapped-delay line filter is provided for operating tap weight coefficients on the incoming data sequence and detecting therefrom a desired signal. A threshold decision circuit performs a threshold decision on the detected desired signal and a decision error of the threshold decision circuit is detected. Tap weight update circuitry updates the tap weight coefficients with the decision error. Tap weight constraining circuitry uses the synchronized chip sequence for constraining a vector of the updated tap weight coefficients to a plane orthogonal to a vector of the synchronized chip sequence and supplies the constrained vector to the tapped-delay line filter as the tap weight coefficients.
According to a third aspect, the present invention provides a method of detecting synchronization between a spread data sequence and a despreading chip sequence, comprising the steps of (a) storing, in a memory, chip samples representing amplitudes of the chip sequence sampled at intervals smaller than chip intervals of the chip sequence, (b) reading, from the memory, a set of chip samples spaced from each other by the chip intervals and spaced from corresponding chip samples of adjacent sets by the smaller intervals, (c) detecting a match or a mismatch between the read chip samples and an incoming spread spectrum data sequence, and (d) despreading the data sequence with the read chip samples if there is a match between the read chip samples and the data sequence. The steps (b) and (c) are repeated on a next set of chip samples of the memory if they mismatch.
According to a fourth aspect, the present invention provides a method of detecting synchronization between a spread data sequence and a despreading chip sequence, comprising the steps of (a) storing, in a memory, chip samples representing amplitudes of the chip sequence sampled at intervals smaller than chip intervals of the chip sequence, (b) reading, from the memory, a set of chip samples spaced from each other by the chip intervals and spaced from corresponding chip samples of adjacent sets by the smaller intervals, (c) detecting a match or a mismatch between the read chip samples and an incoming spread spectrum data sequence, (d) determining the read chip samples as a synchronized chip sequence if they match, and repeating the steps (b) and (c) on a next set of chip samples of the memory if they mismatch, (e) supplying a vector of tap weight coefficients to a tapped-delay line filter and operating the vector on the incoming data sequence to cancel interference signals and detect a desired signal, (f) making a threshold decision on the desired signal, (g) detecting a decision error of the step (f), (h) updating the tap weight coefficients with the decision error, and (i) constraining a vector of the updated tap weight coefficients to a plane orthogonal to a vector of the synchronized chip sequence, and repeating the steps (e) to (h) by using the constrained vector as the tap weight coefficients.